preliminary product description 1 eds-101845 rev f 303 technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com the information provided herein is believed to be reliable at press time. sirenza microdevices assumes no responsibility for i naccuracies or omissions. sirenza microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user?s own risk. prices and specifications are subject to chang e without notice. no patent rights or licenses to any of the circuits described herein are implied or granted to any third party. sirenza microdevices does not authorize or warrant any sirenza microdevices product for use in lif e-support devices and/or systems. copyright 2003 sirenza microdevices, inc. all worldwide rights reserved. [1] 100% tested - insertion gain tested using a 50 ohm contact board (no matching circuitry) during final production test. [2] sample tested - samples pulled from each wafer/package lot. sample test specifications are based on statistical data fro m sample test measurements. the test fixture is an engineering application circuit board (parts are pressed down on the circuit board). the application circuit represents a t rade-off between the optimal noise match and input return loss. 0 5 10 15 20 25 30 35 40 012345678 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 sga-8343 SGA-8343Z low noise, high gain sige hbt product features ? now available in lead free, rohs compliant, & green packaging ? dc-6 ghz operation ? 0.9 db nf min @ 0.9 ghz ? 24 db gmax @ 0.9 ghz ?|g opt |=0.10 @ 0.9 ghz ? oip3 = +28 dbm, p1db = +9 dbm ? low cost, high performance, versatility applications ? analog and digital wireless systems ? 3g, cellular, pcs, rfid ? fixed wireless, pager systems ? driver stage for low power applica- tions ? oscillators sirenza microdevices? sga-8343 is a high performance silicon germanium heterostructure bipolar transistor (sige hbt) designed for operation from dc to 6 ghz. the sga-8343 is optimized for 3v operation but can be biased at 2v for low-voltage battery operated systems. the device provides high gain, low nf, and excellent linearity at a low cost. it can be operated at very low bias currents in applications where high linearity is not required. the matte tin finish on sirenza?s lead-free package utilizes a post annealing process to mitigate tin whisker formation and is rohs compliant per eu directive 2002/95. this package is also manufactured with green molding compounds that contain no antimony trioxide nor halogenated fire retardants. frequency (ghz) gain, gmax (db) gmax gain nf min (db) nf min l o b m y s s c i t s i r e t c a r a h c e c i v e d s n o i t i d n o c t s e t v e c i , v 3 = q c c 5 2 , a m 0 1 = ) d e t o n e s i w r e h t o s s e l n u ( y c n e u q e r f t s e t s t i n u . n i m . p y t . x a m g x a m n i a g e l b a l i a v a m u m i x a mz s z = s z , * l z = l * z h g 9 . 0 z h g 9 . 1 z h g 4 . 2 b d 9 . 3 2 3 . 9 1 7 . 7 1 f ne r u g i f e s i o n m u m i n i mz s a m m a g = t p o z , l z = l * z h g 9 . 0 z h g 9 . 1 z h g 4 . 2 b d 4 9 . 0 0 1 . 1 8 1 . 1 s 1 2 n i a g n o i t r e s n i ] 1 [ z s z = l s m h o 0 5 =z h g 9 . 0b d0 . 1 20 . 2 20 . 3 2 f ne r u g i f e s i o n ] 2 [ n o i t a c i l p p a a n l d r a o b t i u c r i c z h g 9 . 1b d0 4 . 15 7 . 1 n i a gn i a g ] 2 [ n o i t a c i l p p a a n l d r a o b t i u c r i c z h g 9 . 1b d5 . 5 15 . 6 15 . 7 1 p i o 3 t n i o p t p e c r e t n i r e d r o d r i h t t u p t u o ] 2 [ n o i t a c i l p p a a n l d r a o b t i u c r i c z h g 9 . 1m b d8 . 5 28 . 7 2 p b d 1 t n i o p n o i s s e r p m o c b d 1 t u p t u o ] 2 [ n o i t a c i l p p a a n l d r a o b t i u c r i c z h g 9 . 1m b d5 . 70 . 9 h e f n i a g t n e r r u c c d 0 2 10 8 10 0 3 v b o e c e g a t l o v n w o d k a e r b r e t t i m e - r o t c e l l o c v7 . 50 . 6 h t re c n a t s i s e r l a m r e h td a e l - o t - n o i t c n u j o w / c0 0 2 v e c e g a t l o v g n i t a r e p or e t t i m e - r o t c e l l o cv0 . 4 i e c t n e r r u c g n i t a r e p or e t t i m e - r o t c e l l o ca m0 5 typical performance - 3v, 10ma pb rohs compliant & packag e green
sga-8343 low noise sige hbt 2 eds-101845 rev f 303 technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com absolute maximum ratings typical performance - engineering application circuits (see app note an-044) refer to the application note for additional rf data, pcb layouts, boms, biasing instructions, and other key issues to be considered. for the latest application note please visit our site at www.sirenza.com. [3] p out = 0 dbm per tone, 1mhz tone spacing q e r f ) z h g ( v e c ) v ( i q c ) a m ( f n n i m ] 4 [ ) b d ( x a m g ) b d ( b d 1 p ] 5 [ ) m b d ( 3 p i o ] 6 [ ) m b d ( 0 9 . 0 20 10 9 . 07 . 3 20 15 2 30 14 9 . 09 . 3 23 19 2 0 9 . 1 20 15 0 . 11 . 9 10 15 2 30 10 1 . 13 . 9 13 19 2 0 4 . 2 20 15 1 . 14 . 7 10 15 2 30 18 1 . 17 . 7 13 19 2 [4] z s = opt , z l =z l *, the input matching circuit losses have been de-emebedded. [5] z s =z sopt , z l =z lopt , where z sopt and z lopt have been tuned for max p1db (current allowed to drive-up with constant v ce ) [6] z s =z sopt , z l =z lopt , where z sopt and z lopt have been tuned for max oip3 note: optimum nf, p1db, and oip3 performance cannot be achieved simultaneously. peak rf performance under optimum matching conditions r e t e m a r a pl o b m y se u l a vt i n u r o t c e l l o ct n e r r u ci e c 2 7a m t n e r r u c e s a bi b 1a m e g a t l o v r e t t i m e - r o t c e l l o cv ce 5v e s a b - r o t c e l l o ce g a t l o vv b c 2 1v e g a t l o v e s a b - r e t t i m ev b e 5 . 4v r e w o p t u p n i f rp n i 5m b d e g n a r e r u t a r e p m e t e g a r o t st r o t s 0 5 1 + o t 0 4 -c n o i t a p i s s i d r e w o pp s s i d 0 5 3w m e r u t a r e p m e t n o i t c n u j g n i t a r e p ot j 0 5 1 +c e s u a c y a m s t i m i l e s e h t f o e n o y n a d n o y e b e c i v e d s i h t f o n o i t a r e p o e c i v e d e h t , n o i t a r e p o s u o u n i t n o c e l b a i l e r r o f . e g a m a d t n e n a m r e p s e u l a v g n i t a r e p o m u m i x a m e h t d e e c x e t o n t s u m t n e r r u c d n a e g a t l o v . 1 e g a p n o e l b a t e h t n i d e i f i c e p s z sopt e b c z lopt junction temperature calculation mttf is inversely proportional to the device junction temperature. for junction temperature and mttf consid- erations the device operating conditions should also satisfy the following expression: p dc < (t j - t l ) / r th where: p dc = i ce * v ce (w) t j = junction temperature (c) t l = lead temperature (pin 2) (c) r th = thermal resistance (c/w) biasing details the sga-8343 should be biased through a dropping resistor or with active bias circuitry to prevent thermal runaway and combat beta variation. for passive biasing it is recommended that the voltage drop be at least 20% of v ce . a voltage divider from collector-to-base is preferred over a simple series resistor. the effect of beta variation can be minimized by bleeding ~10*i b through the shunt resistor. q e r f ) z h g ( s v ) v ( v e c ) v ( i q c ) a m ( f n ) b d ( n i a g ) b d ( b d 1 p ) m b d ( 3 p i o ] 3 [ ) m b d ( 1 1 s ) b d ( 2 2 s ) b d ( s t n e m m o c 0 9 . 00 . 50 . 32 15 2 . 12 . 8 193 . 7 26 1 -8 1 -k c a b d e e f s e i r e s 5 7 5 . 13 . 37 . 20 15 2 . 17 . 5 18 . 65 . 6 20 1 -5 2 -1 6 0 - n a e e s 0 9 . 10 . 50 . 32 14 . 15 . 6 198 . 7 29 -4 2 - 0 4 . 23 . 37 . 20 16 . 14 . 4 195 . 7 23 1 -4 2 -
sga-8343 low noise sige hbt 3 eds-101845 rev f 303 technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com typical performance - de-embedded s-parameters note: s-parameters are de-embedded to the device leads with z s =z l =50 ? . the device was mounted on a 0.010? pcb with plated-thru holes close to pins 2 and 4. de-embedded s-parameters can be downloaded from our website (www.sirenza.com). typical performance - noise parameters - 3v,10ma [7] z s = opt , z l =z l *, nf min is a noise parameter for which the input matching circuit losses have been de-emebedded. the noise parameters were measured using a maury microwave automated tuner system. the device was mounted on a 0.010? pcb with plated- thru holes close to pins 2 and 4. isolation (db) y c n e u q e r f ) z h g ( f n n i m ] 7 [ ) b d ( t p o g a m g n a r n ( ? ? ? ? ? ) x a m g ) b d ( 9 . 04 9 . 00 1 . 0 5 51 1 . 08 8 . 3 2 9 . 11 . 17 1 . 0 5 2 10 1 . 03 3 . 9 1 4 . 28 1 . 13 2 . 0 7 5 19 0 . 06 6 . 7 1 37 2 . 13 2 . 0 9 7 19 0 . 01 0 . 5 1 45 . 19 2 . 0 0 5 1 -2 1 . 04 9 . 1 1 53 7 . 12 4 . 0 2 2 1 -8 1 . 04 8 . 9 62 0 . 25 5 . 0 0 1 1 -4 2 . 02 6 . 8 0 5 10 15 20 25 30 35 40 012345678 -40 -35 -30 -25 -20 -15 -10 -5 0 gain, gmax (db) gain vs frequency (3v,10ma) frequency (ghz) isolation gmax gain s11,s22 vs frequency (3v,10ma) 0.0 0.2 0.5 1.0 2.0 5.0 0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0 1 ghz 4 ghz 8 ghz 6 ghz 3 ghz 2 ghz s11 s22 opt (3v,10ma) 0.0 0.2 0.5 1.0 2.0 5.0 0.2 0.5 1.0 2.0 5.0 inf 0.2 0.5 1.0 2.0 5.0 0.9 ghz 4 ghz 5 ghz 6 ghz 3 ghz 1.9 ghz 2.4 ghz 0 0.4 0.8 1.2 1.6 2 2.4 01234567 0 5 10 15 20 25 30 nf min (db) g as (db) f min g as minimum noise figure (3v,10ma) frequency (ghz)
sga-8343 low noise sige hbt 4 eds-101845 rev f 303 technology court, broomfield, co 80021 phone: (800) smi-mmic http://www.sirenza.com # n i pn o i t c n u fn o i t p i r c s e d 1e s a bs a i b e s a b / t u p n i f r 2r e t t i m ee c u d e r o t s e l o h a i v e l p i t l u m e s u . d n u o r g o t n o i t c e n n o c . e c n a t c u d n i r e t t i m e 3r o t c e l l o cs a i b r o t c e l l o c / t u p t u o f r 4r e t t i m e2 n i p s a e m a s pin description caution: esd sensitive appropriate precautions in handling, packaging and testing devices must be observed. r e b m u n t r a pe z i s l e e rl e e r / s e c i v e d 3 4 3 8 - a g s" 70 0 0 3 z 3 4 3 8 - a g s" 70 0 0 3 part number ordering information the part will be symbolized with the ?a83? or ?a83z? designator and a dot signifying pin 1 on the top surface of the package. part symbolization use multiple plated-through vias holes located close to the package pins to ensure a good rf ground connection to a continuous groundplane on the backside of the board. recommended pcb layout sot-343 package plated thru holes (0.020" dia) ground plane l c 5. die is facing up for mold and facing down 2.25 l c 6. package surface to be mirror finish. for trim/form. ie :reverse trim/form. symbol 4. all specifications comply to eiaj sc70. 2. dimensions are inclusive of plating. 3. dimensions are exclusive of mold flash 1. all dimensions are in millimeters. & metal burr. note: 0.25 0.10 0.10 0.00 0.80 1.80 0.80 1.85 1.15 min b c e q1 a2 a1 he a d e 0.65 bsc 0.40 0.18 0.40 0.10 1.00 2.40 1.10 1.35 max l 0.10 0.30 b1 0.55 0.70 d e he a2 e e b b1 l c q1 a a1 package dimensions a83 1 4 2 3 1 4 2 3 a83 a83z marking
|
